1. Field of the Invention
The present invention relates to a memory structure and method of fabricating the memory structure, and more particularly, to a two bit memory structure having floating gates with a U-shaped bottom and a method of making the two bit memory structure.
2. Description of the Prior Art
A flash memory is a memory device that allows multiple data writing, reading, and erasing operations. It is a technology that is used widely, and primarily used for portable products. As electronic devices become smaller, the size of the flash memory cells is also shrinking. Currently, scaling down of flash memory cells is considered critical in continuing the trend toward higher device density.
FIG. 1 shows a structure of a two-bit flash memory cell according to the prior art. As shown in FIG. 1, the structure of the conventional two-bit flash memory cell comprises: a substrate 10, a control gate 12 positioned on the substrate 10, floating gates 14a, 14b positioned at two sides of the control gate 12, a dielectric layer 16 positioned between the control gate 12 and the substrate 10 and between the floating gates 14a, 14b and the substrate 10, a dielectric layer 18 positioned between the control gate 12 and the floating gates 14a, 14b, a source/drain doping region 20 positioned in the substrate 10 at a side of the floating gates 14a, 14b, a pocket doping region 22 adjacent to the source/drain doping region 20 and a floating gate channel 24. The pocket doping region 22 is formed by implanting dopants into the pocket doping region 22 and heating up the dopants to make the dopants diffuse laterally.
The structure of the two-bit flash memory cell mentioned above has the floating gates 14a, 14b positioned at the sidewalls of the control gate 12 in order to store two-bit data. As the sizes of electronic devices are shrinking, the floating gate channel also becomes shorter. The length of the floating gate channel is critical to the performance of the flash memory. Generally speaking, the longer the floating gate channel, the better the performance of the flash memory. As integrity of the devices is increased by scaling down the size of the devices, the floating gate channel is shortened and the performance is thereby decreased. Furthermore, the process window is decreased.
Because the pocket doping region is adjacent to the source/drain doping region, during the fabricating process the pocket doping region will be influenced by the source/drain doping region, leading to problems in process control. Therefore, a new memory structure and a fabricating process are needed to improve the control problem and increase the performance of the flash memory.